Table Comparison Differences between Concurrent Sequential VHDL Statements

The table below shows comparison and differences between concurrent and sequential VHDL statements. Concurrent and Sequential statements are basic to VHDL programming. These statements can confuse beginner in learning VHDL coding. The basic thing are not explained here such as that concurrent statements are executed in parallel and sequential statements are executed in sequence as the name itself implies.

The table shows where they are used, how they are used and when they are used. The table is not however direct comparision because there is no direct differences as they are meant for different aspect of the programming. However some differences are there and by knowing and viewing there construct in single tabular form might help to learn these construct.

Concurrent Signal Assignment Statements	Sequential Signal Assignment Statements
Clear mapping of language to hardware	Not Clear Mapping of language to Hardware
Can also be used to describe sequential circuit but not recommended
	· Sequential assignment exist only within a Process · Executed in sequence · Order of execution is important
	· Process is a VHDL construct · Process can have sensitivity list · Two types of Process 1.                 Process with Sensitivity list without wait statement 2.                 Process with Wait Statement without sensitivity list
	· wait statement · variable assignment · if statements · case statements · loop statements
·        when ___ else ·        with ___select when	· if( ) then ____ elsif · case __is when · for __ in __ downto __ loop
Simple concurrent assignment statement: C <= ‘2’; C <= A + B after 5ns; C <= A or B after 5 ns;	Sequential signal assignment statement: · Same as Simple Concurrent Assignment Statement · Only different in that they are put inside Process and when put executed in sequence C <= ‘2’; C <= A + B after 5ns; C <= A or B after 5 ns;
	Sequential assignment within Process with Sensitivity List: process(a, b) begin Y <= a or b; end process; · when a or b is changed the process is activated · Incomplete sensitivity means lack of signal declaration in the process’s sensitivity list. · Incomplete sensitivity implies memory In case of Incomplete sensitivity list the output(eg y) retains its previous value
	Sequential assignment within Process with Wait statements:   • wait on • wait until • wait for   eg. process begin Y <= a or b; Wait on a, b; end process Eg. Process Begin Y <= a or b; wait until a, b; end process   eg.   process begin Y <= a or b; Wait for 10ns; end process   · there is no sensitivity list · process automatically starts, executes the statements inside process and waits for signals eg. a and b or for some time duration eg 10ns
Conditional concurrent assignment:   eg.   Y <= a when (s = “00”) else Y <= b when (s = “01”) else   Other eg. (not interrelated)   Y <= “0010” when (s = “10”) else Y <= “0101” when (x(2)=’1’) else Y <= sum when ctrl(2) = ‘0’ else Y <= diff when ctrl(1 downto 0) = “11” else Y <= c and d when ctrl(1 downto 0) = “00” else	IF Statement:   eg.   If (s = “00”) then Y <= a; elsif(s = “01”) then Y <= b; elsif(s = “10”) then Y <= c; else Y <= d; end if;
Selected Signal Assignment Statements:   eg.   with s select Y <= a when “00”, Y <= b when “01”, Y <= c when “10”, Y <= d when others;	Case Statement:   eg.   Case s is when “00” => y<= a; when “10” => y<= b; when “01” => y<= c; when others => y <= d; end case
Both conditional and selected assignment can be used in circuit implementation but preferences should be given as below: ·        Use conditional assignment for preferential input/ output eg. Priority encoder ·        Use selected assignment for truth table implementation eg. decoder
	For Loop   Eg.   for k in 7 downto 0 loop y(k) <= a(i) or b(i); end loop;

 

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